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seccount
- 用VHDL语言设计电子数字秒表。包含相关文件及说明,用户可以在Xilinx ISE 环境下运行。-With VHDL language design digital stopwatch. Contains the corresponding code and all documents. Users can Xilinx ISE environment in operation
rar
- 51单片机实现的时钟,有调时和秒表功能,用vhdl语言实现-51 MCU clock, and stopwatch function when it has been argued, with vhdl language
digital-electronic-clock
- 基于VHDL的数字电子时钟的设计 实现计时,秒表,闹钟功能-VHDL-based design implementation digital electronic clock timer, stopwatch, alarm clock function
stopwatch1
- 用vhdl实现的数字秒表,显示四位值,最大计时时间为99.99s,全部通过验证,并且在FPGA上得到很多的结果-Using vhdl implementation of the digital stopwatch display four values, the maximum time time 99.99s, all validated, and get a lot of the FPGA results
ciphercount
- 一个简单的密码控制的跑表的vhdl代码,6位数码管显示,有顶层文件和底层文件,当密码为:00001111时,为加计数;当密码为:11110000时,为减计数;当密码为:11001100时,停止计数。 -A simple password-controlled stopwatch the vhdl code, 6 digit LED display, a top-level files and the underlying documents, when the password is: 00
VHDLxiaochengxu
- 一些简单的VHDL小程序。 VHDL 小程序源代码: led七段译码 简单调用 秒表 元件例化-Some simple VHDL applet. Small VHDL source code: led seven segment decoding simple example of calling a stopwatch components
miaobiaosheji
- 设计 秒表 VHDL 利用分频 计数 显示等模块实现秒表功能-VHDL design using frequency counts stopwatch display module stopwatch function
clock
- 数字秒表计数 vhdl 译码器 分频器 计数器 报警器-stopwatch counter
watch
- QuartusII 应用vhdl语言,实现秒表的设计,有暂停键,清零键等功能-QuartusII vhdl language, stopwatch design, Pause, cleared key functions
miaobiao
- 实验课编写的vhdl程序,秒表适用!具体功能是开始计时,停止,清零!经实验,完美运行!-Vhdl program written by the Lab, stopwatch applicable! Specific start time, stop, clear! The experiment, a perfect run!
DE2_lcd_clk
- 用VHDL写的在DE2开发板上的LCD实现的秒表程序-DE2 development board LCD stopwatch program written in VHDL
A
- 基于CPLD的VHDL语言数字钟(含秒表)设计及程序 利用一块芯片完成除时钟源、按键、扬声器和显示器(数码管)之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短(设计过程中即可实现时序仿真)、调试方便、故障率低、修改升级容易等特点。-The VHDL language based on CPLD digital clock (including a stopwatch) design and program By usin
watch
- 使用vhdl设计数码管显示的秒表; 能够准确的计时并显示; 开机显示00.00.00; 用户可以随时清零、暂停、计时;最大记时59分钟,最小精确到0.01秒。-Vhdl design digital display stopwatch accurate timing and display boot display 00.00.00 Users can be cleared at any time, suspend, timing 59 minutes maximum chronogra
EDA
- VHDL实现一个整点报时的秒表第一个子程序-VHDL achieve a integral point time of the stopwatch 1
EDAmiaobiao
- 基于VHDL语言的EDA秒表作业设计,包括分频、秒表主体和数码管显示译码器,附有工程文件和管脚信息(EDA大作业西电02105143)-VHDL language based the EDA the stopwatch job design, including divide the stopwatch the main digital display decoder, with the project file and pin information (EDA Job Western Elec
Second_VHDL
- 本程序是用VHDL实现的秒表,通过对主时钟进行分频得到低速时钟,以调试通过,大家可以参考。-This program is implemented with VHDL stopwatch, low-speed clock master clock divider to debug through, we can refer to.
miaobiao
- 用VHDL语言实现对FPGA的程序编写,实现秒表功能。-Using VHDL FPGA program written stopwatch function.
miao-biao
- 基于vhdl实现数字秒表,实验报告完整版,代码可直接应用-The lab report the full version of the code can be applied directly on vhdl digital stopwatch
miaobiao
- 基于Max+plus2软件的Verilog VHDL语言的按键控制数码管显示秒表-Based on Max+plus2 software Verilog VHDL language button control digital display stopwatch
vhdl_miaobiao
- 基于FPGA,VHDL实现秒表功能,利用了分频和计数-FPGA, VHDL-based stopwatch function, the use of divide and count